Increasing quality and achieving power, performance, and area metrics for standard cell and memory IP by utilizing Solido library IP solutions
A resourceful CAD and Application Engineer with 23-year industry experiences in IC design, verification, manufacturing and testing. Currently, Leo is responsible for supporting Solido Characterization Suite and Solido Variation Designer. Leo received his EE master degree of National Chiao Tung University in 1999.
Standard cell and memory library IP form the majority of silicon area in silicon-on-chip (SoC) designs, and are essential to ensuring production silicon meets power and performance requirements, within the targeted silicon area. Today, standard cell and memory teams today face new challenges in design and verification, as well as library integration. Standard cells and memory bit cells are highly replicated components and require high-sigma SPICE verification, which leads to impractical runtimes using traditional brute-force methods. For newer process nodes, this also results in the requirement to characterize standard cells with statistical .lib models, or LVF.
Library IP integration flows have also expanded to include a wide spectrum of design views and formats, such as functional, physical, electrical, and other views. Therefore, IP must be validated to be correct, accurate, and consistent between different views and formats before production usage.
This presentation will cover Solido library IP solutions: an intelligent, ML-enabled solution for design and verification of standard cells and memories, powered by differentiated Solido technologies in Solido Variation Designer, Solido Characterization Suite, and Solido Crosscheck, as well as Analog FastSPICE (AFS).