Getting the Right Answer with Machine Learning - Utilizing Solido Variation Designer for Accurate Variation-aware Design Verification
Jiandong Ge
Jiandong Ge is a highly skilled Senior Application Engineer Consultant with 17 years of experience in the EDA industry. He is an expert in supporting Solido product families, specializing in delivering exceptional customer service and technical support. Throughout his career, Jiandong has demonstrated his dedication to continuous learning and professional development. He holds a Master degree in Electrical & Electronics Engineering and has pursued ongoing training in his field.

Abstract:
Modern silicon design considerations such as mission-critical usage, low voltage operation, and the latest process technologies have expanded the scope of SPICE-level verification. We now require millions or billions of SPICE simulations for many design steps, which brute-force methods are simply not equipped to handle while meeting production schedule deadlines. As a result, IC verification strategies must evolve to cover exponentially more scenarios than before.
Variation-aware SPICE-level verification of designs over process, voltage, and temperature (PVT) corners as well as local variation mismatch is a critical verification step towards achieving successful silicon. This ensures final silicon operates correctly and within power and performance specifications, and is robust enough to handle local and global variation, as well as the range of operating conditions as designed for.
In this session, we discuss how Solido Variation Designer and Analog FastSPICE (AFS) enable verification teams to achieve high accuracy and coverage for variation-aware verification at 3, 4, 5 and 6+ sigma targets. With an AI-powered engine, Variation Designer maximizes the utilization of simulation budgets to achieve accuracy and coverage targets, while improving runtime by orders of magnitude.

Abstract:
This presentation will cover the evolution of features and tools to provide efficiency and acceleration to the verification process as well as the revolution required to take full advantage of collaboration, traceability, and emerging technologies provided by machine learning (ML) and virtually unlimited cloud computing resources.
The content will included :
• How to enhance your current D&V workflow with proven collaboration, requirements traceability, coverage tracking, regression management, and more as inspired by proven technologies from the software world
• How ML can be applied to the analysis of the coverage model using analytical navigation to speed understanding and accelerate closure.
• How ML can complement rules-based systems to improve regression efficiency and debug turn-around times.
• What is required to take full advantage of this kind of massive compute resource scalability with respect to both dynamic reaction and streaming data.

Increasing quality and achieving power, performance, and area metrics for standard cell and memory IP by utilizing Solido library IP solutions
Leo Chang
A resourceful CAD and Application Engineer with 23-year industry experiences in IC design, verification, manufacturing and testing. Currently, Leo is responsible for supporting Solido Characterization Suite and Solido Variation Designer. Leo received his EE master degree of National Chiao Tung University in 1999.

Abstract:
Standard cell and memory library IP form the majority of silicon area in silicon-on-chip (SoC) designs, and are essential to ensuring production silicon meets power and performance requirements, within the targeted silicon area. Today, standard cell and memory teams today face new challenges in design and verification, as well as library integration. Standard cells and memory bit cells are highly replicated components and require high-sigma SPICE verification, which leads to impractical runtimes using traditional brute-force methods. For newer process nodes, this also results in the requirement to characterize standard cells with statistical .lib models, or LVF.
Library IP integration flows have also expanded to include a wide spectrum of design views and formats, such as functional, physical, electrical, and other views. Therefore, IP must be validated to be correct, accurate, and consistent between different views and formats before production usage.
This presentation will cover Solido library IP solutions: an intelligent, ML-enabled solution for design and verification of standard cells and memories, powered by differentiated Solido technologies in Solido Variation Designer, Solido Characterization Suite, and Solido Crosscheck, as well as Analog FastSPICE (AFS).

Vivian Jiang

David Feng


Jimmy Tien

Enabling Your Jump to N3E using the Cloud and Calibre nmDRC
Vivian Jiang, Technical Manager, TSMC
David Feng, Asia Azure HPC/AI Solution Sales Lead, Microsoft
Jimmy Tien, Advanced product engineer, Calibre foundry programs, Siemens EDA

Vivian Jiang
Vivian Jiang is responsible for TSMC’s  OIP Cloud Alliance. She leads the joint development projects among TSMC and worldwide ecosystem partners to create Cloud-optimized design solutions for customer adoption of TSMC’s advanced technologies. “TSMC DRC Sign-Off in the Cloud with Calibre® nmDRC™ software” is the latest example of the Cloud Alliance strategic initiatives. She brings over 20 years of experiences in the semiconductor industry.’’

David Feng
馮立偉先生目前任職於微軟亞洲區－HPC/AI解決方案副總經理一職，專職推廣 Azure 高效能 AI 運算於製造、半導體等產業及領域，參與眾多大型客戶 EDA 上雲專案，同時幫助客戶運用雲端平台打造安全的作業環境. 馮立偉先生在資訊業界超過 25 年經驗，為台灣第一位 Microsoft Security MVP, 先後在美國微軟及台灣微軟任職。2020 年起榮獲美國微軟年度 Platinum Speaker award, 為大中華區各大 HPC/AI 相關研討會講師。

Jimmy Tien
Jimmy is Product engineer in Calibre Design Solutions Foundry Program. Jimmy is accumulating more than 5 years in Siemens EDA, and have 4 years experience in TSMC, and responsible for come out advance physical verification solutions, DRC cloud solution and DFM flow support and maintenance. Jimmy received a master’s degree in Photonics in National Tsing Hua University.

Abstract:
EDA on the cloud- The emergence of the cloud provides IC and systems developers with new ways to address exploding complexity, the need for massive computing capacity, and the challenge of cross-organization collaboration. By leveraging the right partners, architectures, and security practices, the cloud can accelerate product development, improve productivity, and focus resources on the highest-value activities.

Computation is growing faster node over node as Moore’s Law progresses – particularly at the most advanced nodes. Siemens EDA has collaborated with our partners to both demonstrate the improved turn-around times available by leveraging the cloud as well as to capture Cloud Flight Plans (i.e. best known methods) for our joint customers to get the best performance in the cloud.  With the explosion in compute, it is becoming increasing difficult to access the necessary on premise resources to achieve the fast turnaround times needed to intercept the market window for your next design.  With the “infinite” resource pool of the latest technology servers in the cloud, one can not only access the hardware resources needed to maintain your current turn-around time but in fact achieve more design iterations per day allowing more time to optimize your design or shortening your time to tape out. Come learn more about how to take full advantage of the cloud with Calibre.

Solving advanced node verification challenges with AI-powered Custom IC Verification platform from Siemens EDA
Jason Pang
Accumulating more than 15 years in EDA industry, Jason is proficient in Analog simulator and Computer Aided Design.  Serving as the Sr. consultant in Siemens EDA, currently he is responsible for supporting Analog Mixed signal simulator, Solido Variation-aware design and Solido characterization Suite. Jason received his master degree of Computer Science in Yuan-Ze University, in 2008.

Abstract:
The demand for smarter and more reliable electronic systems has exponentially increased across applications targeting consumer, industrial, high-performance computing, medical and automotive systems. The hardware requirements for these intelligent systems have pushed the semiconductor physics envelope to newer and smaller process geometries for better power, performance, and area (PPA).
Attend this session and learn how Siemens EDAs next generation Custom IC Verification platform helps top semiconductor companies address advanced node verification challenges and produce higher-quality silicon designs in shorter design and verification cycles. The session showcases AFS eXTreme technology to speed-up simulation performance for large-post-layout advanced node designs, next-generation Symphony Pro mixed-signal platform to verify complete mixed-signal ICs using digital-centric methodologies, and Solido AI-powered technology for variation-aware high-sigma verification, library characterization, and IP QA, including Solido Variation Designer, Solido Characterization Suite, and Solido Crosscheck.

mPower transistor-level EMIR enables large scale EMIR for confident tape-outs
Alvin Liu
Alvin Liu在2015年12月取得美國亞利桑那大學電機所碩士學位後即加入西門子EDA至今。目前為負責台灣及亞太區Calibre 產品設計解決方案的資深應用工程師。Alvin主要負責聯發科集團Calibre LVS/PERC的技術支援以及亞太區mPower 相關產品評估及客戶支援。

Abstract:
mPower Power Integrity offers both transistor level and gate-level solutions. The transistor-level flow enables rigorous analysis of large-scale analog designs that were not possible before. This new capability allows design teams to replace expensive, engineering-intensive workarounds with consistent, repeatable analyses that enable confident tape-outs.

3DIC Overview and using xSI and Calibre 3DSTACK flow for 3DIC assembly verification
Rony Wang, Account Technology Manager, Siemens EDA
Gordon Chang, R&D Center Deputy Technical Manager, ASE Group

Rony Wang, In charge of IC package solution in Asia-Pacific for Siemens EDA, including Package Verification, Design and Layout. Over 15 years’ experience in IC/system testing filed and more than 4 years’ experience in IC design/package field.

Abstracts:

3DIC is becoming an increasingly popular alternative to traditional IC packages due to their potential to improve performance. However, implementing 3DIC is more complex than designing traditional IC packages, and verifying their assembly is even more challenging. To address these challenges, we will provide an overview of the full 3DIC design flow, highlighting the importance of assembly verification in 3DIC design, and discussing how xSI-3DSTACK flow can be used to implement it effectively. In particularly, we are pleasured to invite Gordon Change from ASE, Inc. to share valuable experience of adopting xSI-3DSTACK flow to develop a validated ADK and enable it for assembly verification in 3DIC design

Eddy Lu

Gerald Hsu

Gerald Hsu, Technical manager of platform marketing division of Computing, Connectivity & Metaverse Business Group, MediaTek

Eddy Lu, Senior Application Engineer, is in charge of HDAP (High Density Advanced Packaging) solutions in SEDA, including Xpedition IC Packaging tools and Calibre 3DSTACK. Eddy has supported customers for building up 2.5D/3DIC verification flows to verify system connectivity, and completing physical layout of advanced Fan-out RDL and Substrate designs.
Eddy Lu是西門子EDA資深應用工程師，負責 HDAP高密度先進封裝解決方案，包括 Xpedition IC 封裝工具和 Calibre 3DSTACK。 Eddy 支援客戶建立 2.5D/3DIC 驗證流程以驗證系統的連接性，並完成先進的Fan-out RDL 和封裝基板的物理佈局。

Abstract:
With the increasing complexity of 2.5D/3D IC designs and their various structures, designers require a comprehensive solution that encompasses planning, physical implementation, and verification. Xpedition Package Designer provides sufficient capacity and excellent performance to handle advanced packaging designs. Moreover, it offers various features that enhance the efficiency of completing layouts and address manufacturing concerns through better metal balancing control. The flexibility of scripting and automation further allows users to build a customized flow. Siemens EDA is pleased to invite Gerald Hsu from Mediatek to join the session and share his insights on how XPD supports packaging design perspective.